Wednesday, December 26, 2007

Processors

This generational and chronological list of Intel microprocessors attempts to present all of Intel's processors from the pioneering 4-bit 4004 (1971) to the present high-end offerings, the 64-bit Itanium 2 (2002) and Intel Core 2 and Xeon 5100 and 7100 series processors (2006). Concise technical data are given for each product.

Intel 4004: first single-chip microprocessor

MCS-4 Family:

  • 4004-CPU
  • 4001-ROM & 4Bit Port
  • 4002-RAM & 4Bit Port
  • 4003-10Bit Shift Registr
  • 4008-Memory+I/O Interface
  • 4009-Memory+I/O Interface

[edit] 4040

  • Introduced 4th Qtr, 1974
  • Clock speed of 500 kHz to 740 kHz using 4 to 5.185 MHz crystals
  • 0.06 MIPS
  • Bus Width 4 bits (multiplexed address/data due to limited pins)
  • PMOS
  • Number of Transistors 3,000 at 10 µm
  • Addressable Memory 640 bytes
  • Program Memory 8 KB
  • Interrupts
  • Enhanced version of 4004

MCS-40 Family:

  • 4040-CPU
  • 4101-1024-bit (256 x 4) Static RAM w/Separate I/O
  • 4201-4MHz Clock Generator
  • 4207/4209/4211-General Purpose Byte I/O Port
  • 4265-Programmable General Purpose I/O Device
  • 4269-Programmable Keyboard Display Device
  • 4289-Standard Memory Interface for MCS-4/40
  • 4308-8192-bit (1024 x 8) ROM w/ 4-bit I/O Ports
  • 4316-16384-bit (2048 x 8) Static ROM
  • 4702-2048-bit (256 x 8) EPROM
  • 4801-5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A

[edit] The 8-bit processors

[edit] 8008

  • Introduced April 1, 1972
  • Clock speed 500 kHz (8008-1: 800 kHz)
  • 0.05 MIPS
  • Bus Width 8 bits (multiplexed address/data due to limited pins)
  • PMOS
  • Number of Transistors 3,500 at 10 µm
  • Addressable memory 16 KB
  • Typical in dumb terminals, general calculators, bottling machines
  • Developed in tandem with 4004
  • Originally intended for use in the Datapoint 2200 terminal

[edit] 8080

[edit] 8085

  • Introduced March 1976
  • Clock speed 5 MHz
  • 0.37 MIPS
  • Bus Width 8 bits data, 16 bits address
  • Number of Transistors 6,500 at 3 µm
  • Assembly language downwards compatible with 8080.
  • Used in Toledo scale. Also was used as a computer peripheral controller - modems, harddisks, etc...
  • CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.
  • High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured two serial I/O connection,3 maskable interupts,1 Non-maskable,1 programmable,status,DMA.

MCS-85 Family:

  • 8085-CPU
  • 8155-RAM+ 3 I/O Ports+Timer
  • 8156-RAM+ 3 I/O Ports+Timer
  • 8185-SRAM
  • 8202-Dynamic RAM Controller
  • 8203-Dynamic RAM Controller
  • 8205-1 Of 8 Binary Decoder
  • 8206-Error Detection & Correction Unit
  • 8207-DRAM Controller
  • 8210-TTL To MOS Shifter & High Voltage Clock Driver
  • 8212-8 Bit I/O Port
  • 8216-4 Bit Paralell Bidirectional Bus Driver
  • 8218/8219-Bus Controller
  • 8222-Dynamic RAM Refresh Controller
  • 8226-4 Bit Paralell Bidirectional Bus Driver
  • 8231-Arithmetic Processing Unit
  • 8232-Floating Point Processor
  • 8237-DMA Controller
  • 8251-Communication Controller
  • 8253-Programmable Interval Timer
  • 8254-Programmable Interval Timer
  • 8255-Programmable Peripheral Interface
  • 8256-Multifunction Support Controller
  • 8257-DMA Controller
  • 8259-Programmable Interrupt Controller
  • 8271-Programmable Floppy Disk Controller
  • 8272-Single/Double Density Floppy Disk Controller
  • 8273-Programmable HDLC/SDLC Protocol Controller
  • 8274-Multi-Protocol Serial Controller
  • 8275-CRT Controller
  • 8276-Small System CRT Controller
  • 8278-Programmable KeyBoard Interface
  • 8279-KeyBoard/Display Controller
  • 8282-8-bit Non-Inverting Latch with Output Buffer
  • 8283-8-bit Inverting Latch with Output Buffer
  • 8291-GPIB Talker/Listener
  • 8292-GPIB Controller
  • 8293-GPIB Transceiver
  • 8294-Data Encryption/Decryption Unit+1 O/P Port
  • 8295-Dot Matrix Printer Controller
  • 8296-GPIB Transceiver
  • 8297-GPIB Transceiver
  • 8355-16,384-bit (2048 x 8) ROM with I/O
  • 8604-4096-bit (512 x 8) PROM
  • 8702-2K-bit (265 x 8 ) PROM
  • 8755-EPROM+2 I/O Ports

[edit] The bit-slice processor

[edit] 3000 Family

Introduced 3rd Qtr, 1974 Members of the family

  • 3001-Microcontrol Unit
  • 3002-2-bit Arithmetic Logic Unit slice
  • 3003-Look-ahead Carry Generator
  • 3205-High-Speed 6-bit Latch
  • 3207-Quad Bipolar-to-MOS Level Shifter and Driver
  • 3208-Hex Sense Amp and Latch for MOS Memories
  • 3210-TTL-to-MOS Level Shifter and High Voltage Clock Driver
  • 3211-ECL-to-MOS Level Shifter and High Voltage Clock Driver
  • 3212-Multimode Latch Buffer
  • 3214-Interrupt Control Unit
  • 3216/3226-Parallel,Inverting Bi-Directional Bus Driver
  • 3222-Refresh Controller for 4K NMOS DRAMs
  • 3232-Address Multiplexer and Refresh Counter for 4K DRAMs
  • 3235-Quad Bipolar-to-MOS Driver
  • 3242-Address Multiplexer and Refresh Counter for 16K DRAMs
  • 3245-Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
  • 3246-Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
  • 3404-High-Speed 6-bit Latch
  • 3408-Hex Sense Amp and Latch for MOS Memories

Bus Width 2-n bits data/address (depending on number of slices used)

[edit] Signal Processor

[edit] 2900 Family

  • 2910-PCM CODEC – µ LAW
  • 2911-PCM CODEC – A LAW
  • 2912-PCM Line Filters
  • 2920-Signal Processor

[edit] Digital Clocks Processor

[edit] 5000 Family

  • 5101-1024-bit (256 x 4) Static RAM
  • 5201/5202-LCD Decoder-Driver
  • 5204-Time Seconds/Date LCD Decoder-Driver
  • 5234-Quad CMOS-to-MOS Level Shifter and Driver for 4K NMOS RAMs
  • 5235-Quad CMOS TTL-to-MOS Level Shifter and Driver for 4K NMOS
  • 5244-Quad CCD Clock Driver
  • 5801-Low Power Oscillator-Divider
  • 5810-Single Chip LCD Time/Seconds/Date Watch Circuit

[edit] Old Memory

[edit] 1xxx Family

  • 1101-256-bit (256 x 1) Static RAM
  • 1402-1024-bit (256 x 4) Dynamic Shift Register
  • 1403-1024-bit (256 x 4) Dynamic Shift Register
  • 1404-1024-bit (256 x 4) Dynamic Shift Register
  • 1405-512-bit (512 x 1) Dynamic Recirculating Shift Register
  • 1406-200-bit (100 x 2) Dynamic Shift Register
  • 1407-200-bit (100 x 2) Dynamic Shift Register (20 Kohm output)
  • 1506-200-bit (100 x 2) Dynamic Shift Register
  • 1507-200-bit (100 x 2) Dynamic Shift Register (20 Kohm output)
  • 1602-2048-bit (256 x 8) Static PROM
  • 1702-2048-bit (256 x 8) Static PROM
  • S714-2048-bit (256 x 8) Static PROM

[edit] 2xxx Family

  • 2101-1024-bit (256 x 4) Static RAM w/Separate I/O
  • 2102-1024-bit (1024 x 1) Static RAM w/Separate I/O
  • 2104-4096-bit (4096 x 1) Dynamic RAM
  • 2105-1024-bit (1024 x 1) Dynamic RAM
  • 2107-4096-bit (4096 x 1) Dynamic RAM
  • 2108-8192-bit (8192 x 1) Dynamic RAM
  • 2109-8192-bit (8192 x 1) Dynamic RAM
  • 2111-1024-bit (256 x 4) Static RAM w/Common I/O
  • 2112-1024-bit (256 x 4) Static RAM w/Common I/O
  • 2114-4096-bit (1024 x 4) Static RAM w/Common I/O
  • 2115-1024-bit (1024 x 1) Static RAM
  • 2116-16,384-bit (16,384 x 1) Dynamic RAM
  • 2117-16,384-bit (16,384 x 1) Dynamic RAM
  • 2118-16,384-bit (16,384 x 1) Dynamic RAM
  • 2125-1024-bit (1024 x 1) Static RAM
  • 2141-4096-bit (4096 x 1) Static RAM w/Separate I/O
  • 2142-4096-bit (1024 x 4) Static RAM w/Common I/O
  • 2147-4096-bit (4096 x 1) Static RAM w/Separate I/O
  • 2148-4096-bit (1024 x 4) Static RAM w/Common I/O
  • 2149-4096-bit (1024 x 4) Static RAM w/Common I/O
  • 2308-8192-bit (1024 x 8) Static ROM
  • 2316-16,384-bit (2048 x 8) Static ROM
  • 2401-2048-bit (1024 x 2) Dynamic Recirculating Shift Register
  • 2405-2048-bit (1024 x 2) Dynamic Recirculating Shift Register
  • 2416-16384-bit (16384 x 1) CCD Memory
  • 2608-8192-bit (1024 x 8) PROM
  • 2616-16,384-bit (2048 x 8) Static PROM
  • 2704-4096-bit (512 x 8) EPROM
  • 2708-4096-bit (512 x 8) EPROM
  • 2716-16384-bit (2048 x 8) Static EPROM
  • 2732-32,768-bit (4096 x 8) EPROM
  • 2758-8192-bit (1024 x 8) Static EPROM w/Single 5V

[edit] 3xxx Family

  • 3301-1024-bit (256 x 4) Static ROM
  • 3302-2048-bit (512 x 4) Static ROM
  • 3304-4096-bit (1024 x 4 or 512 x 8) Static ROM
  • 3322-2048-bit (512 x 4) Static ROM
  • 3324-4096-bit (1024 x 4 or 512 x 8) Static ROM
  • 3601-1024-bit (256 x 4) PROM
  • 3602-2048-bit (512 x 4) PROM
  • 3604-4096-bit (512 x 8) PROM
  • 3605-4096-bit (1024 x 4) PROM
  • 3608-8192-bit (1024 x 8) PROM
  • 3621-1024-bit (256 x 4) PROM
  • 3622-2048-bit (512 x 4) PROM
  • 3624-4096-bit (512 x 8) PROM
  • 3625-4096-bit (1024 x 4) PROM
  • 3628-8192-bit (1024 x 8) PROM
  • 3636-16,384-bit (2048 x 8) PROM

[edit] 7xxx Family

  • 7110-1,048,576-bit Bubble Memory
  • 7220-Bubble Memory Controller for Intel 7110 Bubble Memory
  • 7230-Current Pulse Generator for Intel 7110 Bubble Memory
  • 7242-Dual Formatter/Sense Amplifier for Intel 7110 Bubble
  • 7250-Coil Predriver (CPD) for Intel 7110 Bubble Memory
  • 7254-Driver Transistor for Intel 7110 Bubble Memory

[edit] The 16-bit processors: origin of x86

[edit] 8086

  • Introduced June 8, 1978
  • Clock speeds:
    • 5 MHz with 0.33 MIPS
    • 8 MHz with 0.66 MIPS
    • 10 MHz with 0.75 MIPS
  • The memory is divided into odd and even banks. It accesses both the banks simultaneuosly in order to read 16 bit of data in one clock cycle.
  • Bus Width 16 bits data, 20 bits address
  • Number of Transistors 29,000 at 3 µm
  • Addressable memory 1 megabyte
  • 10X the performance of 8080
  • Used in portable computing
  • Used segment registers to access more than 64 KB of data at once, bane of programmers' existence for years to come

[edit] 8088

  • Introduced June 1, 1979
  • Clock speeds:
    • 5 MHz with 0.33 MIPS
    • 8 MHz with 0.75 MIPS
  • Internal architecture 16 bits
  • External bus Width 8 bits data, 20 bits address
  • Number of Transistors 29,000 at 3 µm
  • Addressable memory 1 megabyte
  • Identical to 8086 except for its 8 bit external bus (hence an 8 instead of a 6 at the end)
  • Used in IBM PCs and PC clones


iAPX 432 (chronological entry)

[edit] 80186

  • Introduced 1982
  • Used mostly in embedded applications - controllers, point-of-sale systems, terminals, and the like
  • Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor
  • Later renamed the iAPX 186

[edit] 80188

  • A version of the 80186 with an 8-bit external data bus
  • Later renamed the iAPX 188

[edit] 80286

  • Introduced February 1, 1982
  • Clock speeds:
    • 6 MHz with 0.9 MIPS
    • 8 MHz, 10 MHz with 1.5 MIPS
    • 12.5 MHz with 2.66 MIPS
    • 16 MHZ, 20MHz and 25MHz available.
  • Bus Width 16 bits
  • Included memory protection hardware to support multitasking operating systems with per-process address space
  • Number of Transistors 134,000 at 1.5 µm
  • Addressable memory 16 MB
  • Added protected-mode features to 8086 with essentially the same instruction set
  • 3-6X the performance of the 8086
  • Widely used in PC clones at the time
  • Can scan the Encyclopædia Britannica in 45 seconds

[edit] 32-bit processors: the non-x86 microprocessors

[edit] iAPX 432

  • Introduced January 1, 1981 as Intel's first 32-bit microprocessor
  • Object/capability architecture
  • Microcoded operating system primitives
  • One tebrabyte virtual address space
  • Hardware support for fault tolerance
  • Two-chip General Data Processor (GDP), consists of 43201 and 43202
  • 43203 Interface Processor (IP) interfaces to I/O subsystem
  • 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
  • 43205 Memory Control Unit (MCU)
  • Architecture and execution unit internal data paths 32 bit
  • Clock speeds:
    • 5 MHz
    • 7 MHz
    • 8 MHz

[edit] i960 aka 80960

  • Introduced April 5, 1988
  • RISC-like 32-bit architecture
  • predominantly used in embedded systems
  • Evolved from the capability processor developed for the BiiN joint venture with Siemens
  • Many variants identified by two-letter suffixes.


80386SX (chronological entry)


80376 (chronological entry)

[edit] i860 aka 80860

[edit] XScale

  • Introduced August 23, 2000
  • 32-bit RISC microprocessor based on the ARM architecture
  • Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.

[edit] 32-bit processors: the 80386 range

[edit] 80386DX

  • Introduced October 17, 1985
  • Clock speeds:
    • 16 MHz with 5 to 6 MIPS
    • 20 MHz with 6 to 7 MIPS, introduced 16 February 1987
    • 25 MHz with 8.5 MIPS, introduced 4 April 1988
    • 33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced 10 April 1989
  • Bus Width 32 bits
  • Number of Transistors 275,000 at 1 µm
  • Addressable memory 4 GB
  • Virtual memory 64 TB
  • First x86 chip to handle 32-bit data sets
  • Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required by Windows 95 and OS/2 Warp
  • Used in Desktop computing
  • Can address enough memory to manage an eight-page history of every person on earth
  • Can scan the Encyclopædia Britannica in 12.5 seconds


80960 (i960) (chronological entry)

[edit] 80386SX

  • Introduced June 16, 1988
  • Clock speeds:
  • Internal architecture 32 bits
  • External data bus width 16 bits
  • External address bus width 24 bits
  • Number of Transistors 275,000 at 1 µm
  • Addressable memory 16 MB
  • Virtual memory 1 TB
  • Narrower buses enable low-cost 32-bit processing
  • Used in entry-level desktop and portable computing

[edit] 80376

  • Introduced January 16, 1989; Discontinued June 15, 2001
  • Variant of 386 intended for embedded systems
  • No "real mode", starts up directly in "protected mode"
  • Replaced by much more successful 80386EX from 1994


80860 (i860) (chronological entry)


80486DX (chronological entry)

[edit] 80386SL

  • Introduced October 15, 1990
  • Clock speeds:
  • Internal architecture 32 bits
  • External bus width 16 bits
  • Number of Transistors 855,000 at 1 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • First chip specifically made for portable computers because of low power consumption of chip
  • Highly integrated, includes cache, bus, and memory controllers


80486SX/DX2/SL, Pentium, 80486DX4 (chronological entries)

[edit] 80386EX

  • Introduced August 1994
  • Variant of 80386SX intended for embedded systems
  • Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
  • On-chip peripherals:
    • Clock and power mgmt
    • Timers/counters
    • Watchdog timer
    • Serial I/O units (sync and async) and parallel I/O
    • DMA
    • RAM refresh
    • JTAG test logic
  • Significantly more successful than the 80376
  • Used aboard several orbiting satellites and microsatellites
  • Used in NASA's FlightLinux project

[edit] 32-bit processors: the 80486 range

[edit] 80486DX

  • Introduced April 10, 1989
  • Clock speeds:
    • 25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
    • 33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced 7 May 1990
    • 50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced 24 June 1991
  • Bus Width 32 bits
  • Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • Level 1 cache of 8 KB on chip
  • Math coprocessor on chip
  • 50X performance of the 8088
  • Used in Desktop computing and servers
  • Family 4 model 3


80386SL (chronological entry)

[edit] 80486SX

  • Introduced April 22, 1991
  • Clock speeds:
  • Bus Width 32 bits
  • Number of Transistors 1.185 million at 1 µm and 900,000 at 0.8 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • Identical in design to 486DX but without math coprocessor
 the first version was 80486DX with disabled mathco in chip and different pins configuration,
if user need math co capabilities, we must add 487SX which was actually an 486DX with
different pins configuration to prevent user install an 486DX instead of 487SX, so
with these configuration 486SX+487SX we had 2 identical CPU with with only 1 turned on)

[edit] 80486DX2

  • Introduced March 3, 1992
  • Clock speeds:
    • 20 MHz
    • 40 MHz
    • 50 MHz
    • 66 MHz
    • 100 MHz

[edit] 80486SL

  • Introduced November 9, 1992
  • Clock speeds:
    • 20 MHz with 15.4MIPS
    • 25 MHz with 19 MIPS
    • 33 MHz with 25 MIPS
  • Bus Width 32 bits
  • Number of Transistors 1.4 million at 0.8 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • Used in notebook computers
  • Family 4 model 3


Pentium (chronological entry)

[edit] 80486DX4

  • Introduced March 7, 1994
  • Clock speeds:
    • 75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
    • 100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
  • Number of Transistors 1.6 million at 0.6 µm
  • Bus width 32 bits
  • Addressable memory 4 GB
  • Virtual memory 64 TB
  • Pin count 168 PGA Package, 208 sq ftP Package
  • Die size 345 mm²
  • Used in high performance entry-level desktops and value notebooks
  • Family 4 model 8

[edit] 32-bit processors: the Pentium ("I")

[edit] Pentium ("Classic")

  • Bus width 64 bits
  • System bus speed 60 or 66 MHz
  • Address bus 32 bits
  • Addressable Memory 4 GB
  • Virtual Memory 64 TB
  • Superscalar architecture brought 5X the performance of the 33 MHz 486DX processor
  • Runs on 5 volts
  • Used in desktops
  • 16 KB of L1 cache
  • P5 - 0.8 µm process technology
    • Introduced March 22, 1993
    • Number of transistors 3.1 million
    • Socket 4 273 pin PGA processor package
    • Package dimensions 2.16" x 2.16"
    • Family 5 model 1
    • Variants
      • 60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
      • 66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
  • P54 - 0.6 µm process technology
  • P54C - 0.35 µm process technology
    • Number of transistors 3.3 million
    • 90 mm² die size
    • Family 5 model 2
    • Variants


80486DX4 (chronological entry)


80386EX (Intel386 EX) (chronological entry)


Pentium Pro (chronological entry)

[edit] Pentium MMX

[edit] 32-bit processors: P6/Pentium M microarchitecture

[edit] Pentium Pro

  • Introduced November 1, 1995
  • Precursor to Pentium II and III
  • Primarily used in server systems
  • Socket 8 processor package (387 pins) (Dual SPGA)
  • Number of transistors 5.5 million
  • Family 6 model 1
  • 0.6 µm process technology
    • 16 KB L1 cache
    • 256 KB integrated L2 cache
    • 60 MHz system bus speed
    • Variants
      • 150 MHz
  • 0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache
    • Number of transistors 5.5 million
    • 512 KB or 256 KB integrated L2 cache
    • 60 or 66 MHz system bus speed
    • Variants
      • 166 MHz (66 MHz bus speed, 512 KB 0.35 µm cache) Introduced November 1, 1995
      • 180 MHz (60 MHz bus speed, 256 KB 0.6 µm cache) Introduced November 1, 1995
      • 200 MHz (66 MHz bus speed, 256 KB 0.6 µm cache) Introduced November 1, 1995
      • 200 MHz (66 MHz bus speed, 512 KB 0.35 µm cache) Introduced November 1, 1995
      • 200 MHz (66 MHz bus speed, 1 MB 0.35 µm cache) Introduced August 18, 1997

[edit] Pentium II

[edit] Celeron (Pentium II-based)


Pentium II Xeon (chronological entry)

[edit] Pentium III

[edit] Pentium II and III Xeon

  • PII Xeon
  • PIII Xeon
    • Introduced October 25, 1999
    • Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm)
    • L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
    • Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
    • System Bus Speed 133 MHz (256 KB L2 cache) or 100 MHz (1 - 2 MB L2 cache)
    • System Bus Width 64 bit
    • Addressable memory 64 GB
    • Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1 - 2 MB L2)
    • Family 6 model 10
    • Variants

[edit] Celeron (Pentium III Coppermine-based)


XScale (chronological entry)


Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)

  • Introduced April 2000 – July 2002
  • See main entries

[edit] Celeron (Pentium III Tualatin-based)

  • Tualatin Celeron - 0.13 µm process technology
    • 32 KB L1 cache
    • 256 KB Advanced Transfer L2 cache
    • 100 MHz system bus speed
    • Family 6 model 11
    • Variants
      • 1.0 GHz
      • 1.1 GHz
      • 1.2 GHz
      • 1.3 GHz
      • 1.4 GHz

[edit] Pentium M

  • Banias 0.13 µm process technology
    • Introduced March 2003
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
    • Number of transistors 77 million
    • Micro-FCPGA, Micro-FCBGA processor package
    • Heart of the Intel mobile "Centrino" system
    • 400 MHz Netburst-style system bus
    • Family 6 model 9
    • Variants
      • 900 MHz (Ultra low voltage)
      • 1.0 GHz (Ultra low voltage)
      • 1.1 GHz (Low voltage)
      • 1.2 GHz (Low voltage)
      • 1.3 GHz
      • 1.4 GHz
      • 1.5 GHz
      • 1.6 GHz
      • 1.7 GHz
  • Dothan 0.09 µm (90 nm) process technology
    • Introduced May 2004
    • 2 MB L2 cache
    • Revised data prefetch unit
    • 400 MHz Netburst-style system bus
    • 21W TDP
    • Variants
      • 1.00 GHz (Pentium M 723) (Ultra low voltage, 5W TDP)
      • 1.10 GHz (Pentium M 733) (Ultra low voltage, 5W TDP)
      • 1.20 GHz (Pentium M 753) (Ultra low voltage, 5W TDP)
      • 1.30 GHz (Pentium M 718) (Low voltage, 10W TDP)
      • 1.40 GHz (Pentium M 738) (Low voltage, 10W TDP)
      • 1.50 GHz (Pentium M 758) (Low voltage, 10W TDP)
      • 1.60 GHz (Pentium M 778) (Low voltage, 10W TDP)
      • 1.40 GHz (Pentium M 710)
      • 1.50 GHz (Pentium M 715)
      • 1.60 GHz (Pentium M 725)
      • 1.70 GHz (Pentium M 735)
      • 1.80 GHz (Pentium M 745)
      • 2.00 GHz (Pentium M 755)
      • 2.10 GHz (Pentium M 765)
  • Dothan 533 0.09 µm (90 nm) process technology
    • Introduced Q1 2005
    • Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP
    • Variants
      • 1.60 GHz (Pentium M 730)
      • 1.73 GHz (Pentium M 740)
      • 1.86 GHz (Pentium M 750)
      • 2.00 GHz (Pentium M 760)
      • 2.13 GHz (Pentium M 770)
      • 2.26 GHz (Pentium M 780)
  • Stealey 0.09 µm (90 nm) process technology
    • Introduced Q2 2007
    • 512 KB L2, 3-6W TDP
    • Variants
      • 600 MHz (A100)
      • 800 MHz (A110)

[edit] Celeron M

  • Banias-512 0.13 µm process technology
    • Introduced March 2003
    • 64 KB L1 cache
    • 512 KB L2 cache (integrated)
    • SSE2 SIMD instructions
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Family 6 model 9
    • Variants
      • 310 - 1.20 GHz
      • 320 - 1.30 GHz
      • 330 - 1.40 GHz
      • 340 - 1.50 GHz
  • Dothan-1024 90 nm process technology
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • SSE2 SIMD instructions
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Variants
      • 350 - 1.30 GHz
      • 350J - 1.30 GHz, with Execute Disable bit
      • 360 - 1.40 GHz
      • 360J - 1.40 GHz, with Execute Disable bit
      • 370 - 1.50 GHz, with Execute Disable bit
        • Family 6, Model 13, Stepping 8[1]
      • 380 - 1.60 GHz, with Execute Disable bit
      • 390 - 1.70 GHz, with Execute Disable bit
  • Yonah-1024 65 nm process technology
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • SSE3 SIMD instructions, 533MHz front-side bus, execute-disable bit
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Variants
      • 410 - 1.46 GHz
      • 420 - 1.60 GHz,
      • 423 - 1.06 GHz (ultra low voltage)
      • 430 - 1.73 GHz
      • 440 - 1.86 GHz
      • 443 - 1.20 GHz (ultra low voltage)
      • 450 - 2.00 GHz
  • Merom-1024 65 nm process technology
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • SSE3 SIMD instructions, 533MHz front-side bus, execute-disable bit, 64-bit
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Variants
      • 520 - 1.60 GHz

[edit] Intel Core

  • Yonah 0.065 µm (65 nm) process technology
    • Introduced January 2006
    • 667 MHz frontside bus
    • 2 MB (Shared on Duo) L2 cache
    • SSE3 SIMD instructions
    • Variants:
      • Intel Core Duo T2700 2.33 GHz
      • Intel Core Duo T2600 2.16 GHz
      • Intel Core Duo T2500 2.00 GHz
      • Intel Core Duo T2400 1.83 GHz
      • Intel Core Duo T2300 1.66 GHz
      • Intel Core Duo T2050 1.60 GHz
      • Intel Core Solo T1350 1.86 GHz
      • Intel Core Solo T1300 1.66 GHz
      • Intel Core Solo T1200 1.50 GHz [2]

[edit] Dual-Core Xeon LV

  • Sossaman 0.065 µm (65 nm) process technology
    • Introduced March 2006
    • Based on Yonah core, with SSE3 SIMD instructions
    • 667 MHz frontside bus
    • 2 MB Shared L2 cache
    • Variants
      • 2.0 GHz

[edit] Intel Pentium Dual-Core

  • 0.065 µm (65 nm) process technology
    • 533 MHz frontside bus
    • 1 MB Shared L2 cache
    • SSE3 SIMD instructions
    • Variants:
      • Pentium dual-core T2080 1.73 GHz
      • Pentium dual-core T2060 1.60 GHz

[edit] 32-bit processors: NetBurst microarchitecture

[edit] Pentium 4

  • 0.18 µm process technology (1.40 and 1.50 GHz)
    • Introduced November 20, 2000
    • L2 cache was 256 KB Advanced Transfer Cache (Integrated)
    • Processor Package Style was PGA423, PGA478
    • System Bus Speed 400 MHz
    • SSE2 SIMD Extensions
    • Number of Transistors 42 million
    • Used in desktops and entry-level workstations
  • 0.18 µm process technology (1.7 GHz)
    • Introduced April 23, 2001
    • See the 1.4 and 1.5 chips for details
  • 0.18 µm process technology (1.6 and 1.8 GHz)
    • Introduced July 2, 2001
    • See 1.4 and 1.5 chips for details
    • Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
    • Power <1>
    • Used in full-size and then light mobile PCs
  • 0.18 µm process technology Willamette (1.9 and 2.0 GHz)
  • Family 15 model 1
  • Pentium 4 (2 GHz, 2.20 GHz)
  • Pentium 4 (2.4 GHz)
  • 0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6 GHz)
    • Improved branch prediction and other microcodes tweaks
    • 512 KB integrated L2 cache
    • Number of transistors 55 million
    • 400 MHz system bus.
  • Family 15 model 2
  • 0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
  • 0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
    • 800 MHz system bus (all versions include Hyper Threading)
    • 6500 to 10000 MIPS


Itanium (chronological entry)

[edit] Xeon

  • Official designation now Xeon, i.e. not "Pentium 4 Xeon"
  • Xeon 1.4, 1.5, 1.7 GHz
    • Introduced May 21, 2001
    • L2 cache was 256 KB Advanced Transfer Cache (Integrated)
    • Processor Package Style was Organic Lan Grid Array 603 (OLGA 603)
    • System Bus Speed 400 MHz
    • SSE2 SIMD Extensions
    • Used in high-performance and mid-range dual processor enabled workstations
  • Xeon 2.0 GHz and up to 3.6 GHz


Itanium 2 (chronological entry)

[edit] Mobile Pentium 4-M

  • 0.13 µm process technology
  • 55 million transistors
  • cache L2 512 KB
  • BUS a 400 MHz
  • Supports up to 1 GB of DDR 266 MHz Memory
  • Supports ACPI 2.0 and APM 1.2 System Power Management
  • 1.3 V - 1.2 V (SpeedStep)
  • Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
  • Sleep Power 5 W (1.2 V)
  • Deeper Sleep Power = 2.9 W (1.0 V)
    • 1.40 GHz - 23 April 2002
    • 1.50 GHz - 23 April 2002
    • 1.60 GHz - 4 March 2002
    • 1.70 GHz - 4 March 2002
    • 1.80 GHz - 23 April 2002
    • 1.90 GHz - 24 June 2002
    • 2.00 GHz - 24 June 2002
    • 2.20 GHz - 16 September 2002
    • 2.40 GHz - 14 January 2003
    • 2.40 GHz - 14 January 2003
    • 2.50 GHz - 16 April 2003
    • 2.60 GHz - 11 June 2003

[edit] Pentium 4 EE

  • Introduced September 2003
  • EE = "Extreme Edition"
  • Built from the Xeon's "Gallatin" core, but with 2 MB cache

[edit] Pentium 4E

  • Introduced February 2004
  • built on 0.09 µm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MB L2 cache
  • 533 MHz system bus (2.4A and 2.8A only)
  • Number of Transistors 125 million on 1 MB Models
  • Number of Transistors 169 million on 2 MB Models
  • 800 MHz system bus (all other models)
  • Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
  • The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater clock speeds.
  • 7500 to 11000 MIPS
  • LGA-775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)
  • The 6xx series has 2 MB L2 cache and Intel 64

[edit] Pentium 4F

  • Introduced Spring 2004
  • same core as 4E, "Prescott"
  • 3.2–3.6 GHz
  • starting with the D0 stepping of this processor, Intel 64 64-bit extensions has also been incorporated

[edit] 64-bit processors: IA-64

  • New instruction set, not at all related to x86.
  • Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly.

[edit] Itanium

[edit] Itanium 2

  • Released July 2002
  • 900 MHz and 1 GHz


Pentium M (chronological entry)


Pentium 4EE, 4E (chronological entries)

  • Introduced September 2003, February 2004, respectively
  • See main entries

[edit] 64-bit processors: Intel64 - NetBurst

  • Intel® Extended Memory 64 Technology
  • Mostly compatible with AMD's AMD64 architecture
  • Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)

[edit] Pentium 4F, D0 and later steppings

  • Starting with the D0 stepping of this processor, x86-64 extensions are supported

[edit] Pentium D

Main article: List of Intel Pentium D microprocessors
  • Smithfield - 90 nm process technology (2.8–3.4 GHz)
    • Introduced May 26, 2005
    • 2.8–3.4 GHz (model numbers 820-840)
    • Number of Transistors 230 million
    • 1 MB x 2 (non-shared, 2 MB total) L2 cache
    • Cache coherency between cores requires communication over the FSB
    • Performance increase of 60% over similarly clocked Prescott
    • 2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005
  • Presler - 65 nm process technology (2.8–3.6 GHz)
    • Introduced January 16, 2006
    • 2.8–3.6 GHz (model numbers 920-960)
    • Number of Transistors 376 million
    • 2 MB x 2 (non-shared, 4 MB total) L2 cache

[edit] Pentium Extreme Edition

  • Smithfield - 90 nm process technology (3.2 GHz)
    • Variants
      • Pentium 840 EE - 3.20 GHz (2 x 1 MB L2)
  • Presler - 65 nm process technology (3.46, 3.73)
    • 2 MB x 2 (non-shared, 4 MB total) L2 cache
    • Variants
      • Pentium 955 EE - 3.46 GHz
      • Pentium 965 EE - 3.73 GHz

[edit] Xeon

  • Nocona
  • Irwindale
  • Cranford
  • Potomac
    • Introduced April 2005
    • Cranford with 8 MB of L3 cache
  • Paxville DP (2.8 GHz)
    • Introduced October 10, 2005
    • Dual-core version of Irwindale, with 4 MB of L2 Cache (2 MB per core)
    • 2.8 GHz
    • 800 MT/s front side bus
  • Paxville MP - 90 nm process (2.67 - 3.0 GHz)
    • Introduced November 1, 2005
    • Dual-Core Xeon 7000 series
    • MP-capable version of Paxville DP
    • 2 MB of L2 Cache (1 MB per core) or 4 MB of L2 (2 MB per core)
    • 667 MT/s FSB or 800 MT/s FSB
  • Dempsey - 65 nm process (2.67 - 3.73 GHz)
    • Introduced May 23, 2006
    • Dual-Core Xeon 5000 series
    • MP version of Presler
    • 667 MT/s or 1066 MT/s FSB
    • 4 MB of L2 Cache (2 MB per core)
    • Socket J, also known as LGA 771.
  • Tulsa - 65 nm process (2.5 - 3.4 GHz)
    • Introduced August 29, 2006
    • Dual-Core Xeon 7100-series
    • Improved version of Paxville MP
    • 667 MT/s or 800 MT/s FSB

[edit] 64-bit processors: Intel64 - Intel Core microarchitecture

[edit] Xeon

  • Woodcrest - 65 nm process technology
    • Server and Workstation CPU (SMP support for dual CPU system)
    • Introduced June 26, 2006
    • Dual-Core
    • Intel Virtualization Technology, multiple OS support
    • EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160
    • Execute Disable Bit
    • LaGrande Technology, enhanced security hardware extensions
    • SSSE3 SIMD instructions
    • iAMT2 (Intel Active Management Technology), remotely manage computers
    • Variants
      • Xeon 5160 - 3.00 GHz (4 MB L2, 1333 MHz FSB, 80 W)
      • Xeon 5150 - 2.66 GHz (4 MB L2, 1333 MHz FSB, 65 W)
      • Xeon 5140 - 2.33 GHz (4 MB L2, 1333 MHz FSB, 65 W)
      • Xeon 5130 - 2.00 GHz (4 MB L2, 1333 MHz FSB, 65 W)
      • Xeon 5120 - 1.86 GHz (4 MB L2, 1066 MHz FSB, 65 W)
      • Xeon 5110 - 1.60 GHz (4 MB L2, 1066 MHz FSB, 65 W)
      • Xeon 5148LV - 2.33 GHz (4 MB L2, 1333 MHz FSB, 40 W) -- Low Voltage Edition


  • Clovertown - 65 nm process technology
    • Server and Workstation CPU (SMP support for dual CPU system)
    • Introduced Dec 13th 2006
    • Quad-Core
    • Intel Virtualization Technology, multiple OS support
    • EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160
    • Execute Disable Bit
    • LaGrande Technology, enhanced security hardware extensions
    • SSSE3 SIMD instructions
    • iAMT2 (Intel Active Management Technology), remotely manage computers
    • Variants
      • Xeon X5355 - 2.66 GHz (2x4 MB L2, 1333 MHz FSB, 105 W)
      • Xeon E5345 - 2.33 GHz (2x4 MB L2, 1333 MHz FSB, 80 W)
      • Xeon E5335 - 2.00 GHz (2x4 MB L2, 1333 MHz FSB, 80 W)
      • Xeon E5320 - 1.86 GHz (2x4 MB L2, 1066 MHz FSB, 65 W)
      • Xeon E5310 - 1.60 GHz (2x4 MB L2, 1066 MHz FSB, 65 W)
      • Xeon L5320 - 1.86 GHz (2x4 MB L2, 1066 MHz FSB, 40 W)-- Low Voltage Edition

[edit] Intel Core 2

  • Conroe - 65 nm process technology
    • Desktop CPU (SMP support restricted to 2 CPUs)
    • Two CPUs in one package
    • Introduced July 27, 2006
    • SSSE3 SIMD instructions
    • Number of Transistors 291 Million on 4 MB Models
    • Number of Transistors 167 Million on 2 MB Models
    • Intel Virtualization Technology, multiple OS support
    • LaGrande Technology, enhanced security hardware extensions
    • Execute Disable Bit
    • EIST (Enhanced Intel SpeedStep Technology)
    • iAMT2 (Intel Active Management Technology), remotely manage computers
    • LGA775
    • Variants
      • Core 2 Duo E6850 - 3.00 Ghz (4 MB L2, 1333 MHz FSB)
      • Core 2 Duo E6800 - 2.93 Ghz (4 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6750 - 2.67 GHz (4 MB L2, 1333 MHz FSB)
      • Core 2 Duo E6700 - 2.67 GHz (4 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6650 - 2.33 GHz (4 MB L2, 1333 MHz FSB)
      • Core 2 Duo E6600 - 2.40 GHz (4 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6420 - 2.13 GHz (4 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6400 - 2.13 GHz (2 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6320 - 1.86 GHz (4 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6300 - 1.86 GHz (2 MB L2, 1066 MHz FSB)
      • Core 2 Duo E4500 - 2.20 GHz (2 MB L2, 800 MHz FSB, no VT)
      • Core 2 Duo E4400 - 2.00 GHz (2 MB L2, 800 MHz FSB, no VT)
      • Core 2 Duo E4300 - 1.80 GHz (2 MB L2, 800 MHz FSB, no VT)


  • Conroe XE - 65 nm process technology
    • Desktop Extreme Edition CPU (SMP support restricted to 2 CPUs)
    • Introduced July 27, 2006
    • same features as Conroe
    • LGA775
    • Variants
      • Core 2 Extreme X6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB)


  • Merom - 65 nm process technology
    • Mobile CPU (SMP support restricted to 2 CPUs)
    • Introduced July 27, 2006
    • same features as Conroe
    • Socket M
    • Variants
      • Core 2 Duo T7700 - 2.40 GHz (4 MB L2, 800 MHz FSB) (Santa Rosa platform)
      • Core 2 Duo T7600 - 2.33 GHz (4 MB L2, 667 MHz FSB)
      • Core 2 Duo T7500 - 2.20 GHz (4 MB L2, 800 MHz FSB)
      • Core 2 Duo T7400 - 2.16 GHz (4 MB L2, 667 MHz FSB)
      • Core 2 Duo T7300 - 2.00 GHz (4 MB L2, 800 MHz FSB)
      • Core 2 Duo T7200 - 2.00 GHz (4 MB L2, 667 MHz FSB)
      • Core 2 Duo T7100 - 1.80 GHz (2 MB L2, 800 Mhz FSB)
      • Core 2 Duo T5600 - 1.83 GHz (2 MB L2, 667 MHz FSB)
      • Core 2 Duo T5500 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
      • Core 2 Duo T5200 - 1.60 GHz (2 MB L2, 533 MHz FSB)
      • Core 2 Duo L7500 - 1.60 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
      • Core 2 Duo L7400 - 1.50 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
      • Core 2 Duo L7300 - 1.40 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
      • Core 2 Duo L7200 - 1.33 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
      • Core 2 Duo U7600 - 1.20 GHz (2 MB L2, 533 MHz FSB) (Ultra mobile)
      • Core 2 Duo U7500 - 1.06 GHz (2 MB L2, 533 MHz FSB) (Ultra mobile)


  • Kentsfield - 65 nm process technology
    • Desktop CPU Quad Core (SMP support restricted to 4 CPUs)
    • Introduced December 13, 2006
    • same features as Conroe but with 4 CPU Cores
    • Socket 775
    • Variants
      • Core 2 Extreme QX6800 - 2.93 GHz (2x4 MB L2, 1066 MHz FSB) (Apr 9th 07)
      • Core 2 Extreme QX6700 - 2.66 GHz (2x4 MB L2, 1066 MHz FSB) (Nov 14th 06)
      • Core 2 Quad Q6600 - 2.40 GHz (2x4 MB L2, 1066 MHz FSB) (Jan 7th 07)

[edit] Detailed x86 architecture microprocessor lists

[edit] Intel 805xx product codes

Intel discontinued the use of part numbers such as 80486 in the marketing of mainstream x86-architecture microprocessors with the introduction of the Pentium brand in 1993. However, numerical codes, in the 805xx range, continued to be assigned to these processors for internal and part numbering uses. The following is a list of such product codes in numerical order:

Product code Marketing name(s) Codename(s)
80500 Pentium P5 (A-step)
80501 Pentium P5
80502 Pentium P54C, P54CS
80503 Pentium MMX P55C, Tillamook
80521 Pentium Pro P6
80522 Pentium II Klamath
80523 Pentium II, Celeron, Pentium II Xeon Deschutes, Covington, Drake
80524 Pentium II, Celeron Dixon, Mendocino
80525 Pentium III, Pentium III Xeon Katmai, Tanner
80526 Pentium III, Celeron, Pentium III Xeon Coppermine, Cascades
80528 Pentium 4, Xeon Willamette (Socket 423), Foster
80530 Pentium III, Celeron Tualatin
80531 Pentium 4, Celeron Willamette (Socket 478)
80532 Pentium 4, Celeron, Xeon Northwood, Prestonia, Gallatin
80535 Pentium M, Celeron M Banias
80536 Pentium M, Celeron M Dothan
80537 Core 2 Duo T-series Merom
80538 Core Solo, Celeron M 4xx Yonah
80539 Core Duo Yonah
80541 Itanium Merced
80546 Pentium 4, Celeron D, Xeon Prescott (Socket 478), Nocona, Irwindale, Cranford, Potomac
80547 Pentium 4, Celeron D Prescott (LGA775)
80550 Dual-Core Xeon 71xx Tulsa
80551 Pentium D, Pentium EE, Dual-Core Xeon Smithfield, Paxville DP
80552 Pentium 4, Celeron D Cedar Mill
80553 Pentium D, Pentium EE Presler
80555 Dual-Core Xeon 50xx Dempsey
80556 Dual-Core Xeon 51xx Woodcrest
80557 Core 2 Duo E-series, Dual-Core Xeon 30xx Conroe
80560 Dual-Core Xeon 70xx Paxville MP
80562 Core 2 Quad, Core 2 Extreme QX-series, Quad-Core Xeon 32xx Kentsfield
80563 Quad-Core Xeon 53xx Clovertown

Posted by Mohit at 4:59 AM 0 comments

Processors

Athlon is the brand name applied to a series of different x86 processors designed and manufactured by AMD. The original Athlon, or Athlon Classic, was the first seventh-generation x86 processor and, in a first, retained the initial performance lead it had over Intel's competing processors for a significant period of time. AMD has continued the Athlon name with the Athlon 64, an eighth-generation processor featuring AMD64 (later renamed x86-64) technology.

The Athlon made its debut on June 23, 1999. The name was chosen by AMD as short for "decathlon". Athlon was the ancient Greek word for "Champion/trophy of the games".

General Architecture

Internally, the Athlon is a fully seventh generation x86 processor, the first of its kind. The CPU was designed by a combination of AMD engineers and ex-DEC engineers. The result was a merging of technologies from AMD's earlier CPUs and the DEC Alpha 21264.

Like the AMD K5 and K6, the Athlon is a RISC microprocessor which decodes x86 instructions into its own internal instructions at runtime. The CPU is an out-of-order design, like previous post-5x86 AMD CPUs. The Athlon utilizes the DEC Alpha EV6 bus architecture with double data rate (DDR) technology. This means that at 100 MHz the Athlon front side bus actually transfers at a rate similar to a 200 MHz single data rate bus, like that used on Intel's Pentium III.

AMD designed the CPU with more robust x86 instruction decoding capabilities than that of K6, to enhance its ability to keep more data in-flight at once. Athlon's CISC to RISC decoder triplet could potentially decode 6 x86 operations per clock, although this was somewhat unlikely in real-world use.[1] The critical branch predictor unit, essential to keeping the pipeline busy, was enhanced compared to what was onboard the K6. Deeper pipelining with more stages allowed higher clock speeds to be attained.[2] Whereas the AMD K6-III+ topped out at 570 MHz due to its short pipeline, even when built on the 180 nm process, the Athlon was capable of going much higher.

AMD ended its long-time handicap with floating point x87 performance by designing an impressive super-pipelined, out-of-order, triple-issue floating point unit.[1] Each of its 3 units were tailored to be able to calculate an optimal type of instructions with some redundancy. By having separate units, it was possible to operate on more than one floating point instruction at once.[1] This FPU was a huge step forward for AMD. While the K6 FPU had looked anemic compared to the Intel P6 FPU, with Athlon this was no longer the case.[3]

The 3DNow! floating point SIMD technology, again present, received some revisions and a name change to "Enhanced 3DNow!". Additions included DSP instructions and an implementation of the extended-MMX subset of Intel SSE.[4]

CPU Caching onboard Athlon consisted of the typical two levels. Firstly, Athlon has the largest level 1 cache in x86 history; a 2-way associative cache of 2×64 KiB separated into data and instruction cache (Harvard architecture).[1] This cache was double the size of K6's already large 2×32 KiB cache, and quadruple the size of Pentium II and III's 2×16 KiB L1 cache. Athlon initially used 512 KiB of L2 cache, separate from the CPU, on the cartridge circuit board. This was done because the 250 nm CPU manufacturing processes was too large to allow for on-die cache while maintaining cost-effective die size. Later Athlon CPUs, afforded greater transistor budgets by smaller 180 nm and 130 nm process nodes, moved to on-die L2 cache at full CPU clock speed.

[edit] Athlon

[edit] Athlon Classic

Slot-A Athlon, shown with packaging removed

Athlon Classic launched on June 23, 1999. It showed superior performance compared to the reigning champion, Pentium III, in every benchmark.[5]

Athlon Classic is a cartridge-based processor. The design, called Slot A, was quite similar to but incompatible with Intel's Slot 1 cartridge used for Pentium II and Pentium III. The cartridge allowed use of higher speed cache memory than is possible to put on the motherboard. Like Pentium II and the "Katmai"-core Pentium III, Athlon Classic used a 512 KiB secondary cache. This cache, again like its competitors, ran at a fraction of the core clock rate and had its own 64-bit bus, called a "backside bus" that allowed concurrent system front side bus and cache accesses.[6] Initially the L2 cache was set for half of the CPU clock speed, on up to 700 MHz Athlon CPUs. Faster Slot-A processors were forced to compromise with cache clock speed and ran at 2/5 (up to 850 MHz) or 1/3 (up to 1 GHz).[7] The SRAM available at the time was incapable of matching the Athlon's clock scalability, due both to cache chip technology limitations and electrical/cache latency complications of running an external cache at such a high speed.

The Slot-A Athlons were the first multiplier-locked CPUs from AMD. This was partly done to hinder CPU remarking being done by questionable resellers around the globe. AMD's older CPUs could simply be set to run at whatever clock speed the user chose on the motherboard, making it trivial to relabel a CPU and sell it as a faster grade than it was originally intended. These relabeled CPUs were not always stable, being overclocked and not tested properly, and this was damaging to AMD's reputation. Although the Athlon was multiplier locked, crafty enthusiasts eventually discovered that a connector on the PCB of the cartridge could control the multiplier. Eventually a product called the "Goldfingers device" was created that could unlock the CPU, named after the gold connector pads on the processor board that it attached to.[8]

In commercial terms, the Athlon Classic was an enormous success — not just because of its own merits, but also because the normally dependable Intel endured a series of major production, design, and quality control issues at this time. In particular, Intel's transition to the 180 nm production process, starting in late 1999 and running through to mid-2000, suffered delays. There was a shortage of Pentium III parts. In contrast, AMD enjoyed a remarkably smooth process transition, had ample supplies available, causing Athlon sales to become quite strong.

Specifications

  • -> K7 "Argon" (250 nm)
  • -> K75 "Pluto/Orion" (180 nm)
  • L1-Cache: 64 + 64 KiB (Data + Instructions)
  • L2-Cache: 512 KiB, external chips on CPU module with 50, 40 or 33% of CPU-speed
  • MMX, 3DNow!
  • Slot A (EV6)
  • Front side bus: 200 MT/s (100 MHz double-pumped)
  • VCore: 1.6 V (K7), 1.6 - 1.8 V (K75)
  • First release: June 23, 1999 (K7), November 29 1999 (K75)
  • Clockrate: 500 - 700 MHz (K7), 550 - 1000 MHz (K75)

[edit] Thunderbird (T-Bird)

Athlon "Thunderbird"

The second generation Athlon, the Thunderbird, debuted on June 5, 2000. This version of the Athlon shipped in a more traditional pin-grid array (PGA) format that plugged into a socket ("Socket A") on the motherboard. It was sold at speeds ranging from 600 to 1400 MHz. The major difference, however, was cache design. Just as Intel had done when they replaced the old Katmai Pentium III with the much faster Coppermine P-III, AMD replaced the 512 KiB external reduced-speed cache of the Athlon Classic with 256 KiB of on-chip, full-speed exclusive cache. As a general rule, more cache improves performance, but faster cache improves it further still.[9]

AMD changed cache design significantly with Thunderbird. With the older Athlon CPUs, the CPU caching was of an inclusive design where data from the L1 is duplicated in the L2 cache. Thunderbird moved to an exclusive design where the L1 cache's contents are not duplicated in the L2. This increases total cache size of the processor and effectively makes caching behave as if there is a very large L1 cache with a slower region (the L2) and a very fast region (the L1).[10] Because of Athlon's very large L1 cache and the exclusive design which turns the L2 cache into basically a "victim cache", the need for high L2 performance and size was lessened. AMD kept the 64-bit L2 cache data bus from the older Athlons, as a result, and allowed it to have a relatively high latency. A simpler L2 cache reduced the possibility of the L2 cache causing clock scaling and yield issues. Still, instead of the 2-way associative scheme used in older Athlons, Thunderbird did move to a more efficient 16-way associative layout.[9]

The Thunderbird was AMD's most successful product since the Am386DX-40 ten years earlier. Mainboard designs had improved considerably by this time, and the initial trickle of Athlon mainboard makers had swollen to include every major manufacturer. Their new fab in Dresden came on-line, allowing further production increases, and the process technology was improved by a switch to copper interconnects. In October 2000 the Athlon "C" was introduced, raising the mainboard front side bus speed to 133 MHz (266 MT/s) and providing roughly 10% extra performance per clock over the "B" model Thunderbird.

Specifications

[edit] Athlon XP/MP

Athlon XP logo

In performance terms, the Thunderbird had easily eclipsed the rival Pentium III, and the early Pentium 4 were a long way off the pace, but gradually clawed their way closer. The 1.7 GHz P4 (April 2001) served notice that the Thunderbird could not count on retaining performance leadership forever, and thermal and electricity-consumption issues with the Thunderbird design meant that it was not practical to take it past 1400 MHz (and even at that speed it was rather hot).

[edit] Palomino

Athlon XP "Palomino" 1600+

AMD released the third major Athlon version on October 9, 2001, code-named "Palomino", and named it Athlon XP. The Athlon XP was marketed using a PR rating system, which compared its performance to an Athlon with the "Thunderbird" core. Athlon XP was introduced at speeds between 1333 and 1533 MHz, with ratings from 1500+ to 1800+. At launch, the new core allowed AMD to take the x86 performance lead with the 1800+ model, and enhance that lead with the release of the 1600 MHz 1900+ less than a month later.[11] The "XP" suffix is interpreted to mean eXtreme Performance and also as an unofficial reference to Windows XP.[12]

Palomino was the first K7 core to include the full SSE instruction set from the Intel Pentium III as well as AMD's 3DNow! Professional. It is roughly 10% faster than Thunderbird at the same clock speed, thanks in part to the new SIMD functionality and to several additional improvements. The core has enhancements to the K7's TLB architecture and the addition of a hardware data prefetch mechanism to better take advantage of available memory bandwidth.[13]

Changes in core layout result in Palomino being more frugal with its electrical demands, consuming approximately 20% less power than its predecessor, and thus reducing heat output comparatively as well.[14] While Athlon "Thunderbird" was near its clock ceiling at 1400 MHz, changes to Palomino's transistor layout and the reduction in power demands allowed it to continue increasing clock speed even at the same 180 nm manufacturing process node and core voltage.

The "Palomino" was actually first released as a mobile version, called the Mobile Athlon 4 (codenamed "Corvette").[13] Palomino was also available in a form that officially supports dual processing, known as Athlon MP.[15]

Specifications

[edit] Thoroughbred (T-Bred)

Athlon XP "Thoroughbred A" 1700+

The fourth-generation Athlon, the Thoroughbred, was released 10 June 2002 at 1.8 GHz, or 2200+ on the PR rating system. The "Thoroughbred" core marked AMD's first production 130 nm silicon, resulting in a significant reduction in die size compared to its 180 nm predecessor.

There are two versions of this core, commonly called A and B. The A version was introduced at 1800 MHz, and had some heat and design issues that held its clock scalability back. In fact, AMD wasn't able to increase its clock above Palomino's top grades. Because of this, it was only sold in versions from 1333 to 1800 MHz, replacing the larger Palomino core. The B version of Thoroughbred has an additional metal layer to improve its ability to reach higher clock speeds. It launched at higher clock speeds.

Other than the new manufacturing process, the Thoroughbred design was largely the same as the "Palomino". The Thoroughbred line received an increased front side bus clock during its lifetime, up to 333 MT/s from 266 MT/s. This improved the processor's memory and I/O access efficiency, and improved per-clock performance as a result. AMD shifted their PR rating scheme accordingly, making lower clock speeds equate to higher PR ratings.

Specifications

  • L1-Cache: 64 + 64 KiB (Data + Instructions)
  • L2-Cache: 256 KiB, fullspeed
  • MMX, 3DNow!, SSE
  • Socket A (EV6)
  • Front side bus: 133/166 MHz (266/333 MT/s)
  • VCore: 1.5 V - 1.65 V
  • First release: June 10, 2002 (A), August 21, 2002 (B)
  • Clockrate:
    • T-Bred "A": 1400 - 1800 MHz (1600+ to 2200+)
    • T-Bred "B": 1400 - 2250 MHz (1600+ to 2800+)
    • 133 MHz FSB: 1400 - 2133 MHz (1600+ to 2600+)
    • 166 MHz FSB: 2083 - 2250 MHz (2600+ to 2800+)

[edit] Barton and Thorton

Fifth-generation Athlon Barton-core processors released in early 2003 featured PR ratings of 2500+, 2600+, 2800+, 3000+, and 3200+. While not operating at higher clock rates than Thoroughbred-core processors, they earned their higher PR-rating by featuring a total of 512 KiB L2 cache and, in some models, a faster 400 MT/s front side bus.[16] The Thorton core was a variant of the Barton with half of the L2 cache disabled and thus functionally identical to the Thoroughbred core.

By the time of Barton's release, the "Northwood" Pentium 4 had become more than competitive with AMD's processors.[17] Unfortunately, due to the architecture of AMD's processor caches, an L2 cache increase to 512 KiB did not have nearly the same impact as it did to Intel's line. Only an increase of several percent was gained in per-clock performance.[16] The PR rating became somewhat inaccurate because some Barton models with lower clock rate weren't consistently outperforming their higher-clocked Thoroughbred predecessors with lower ratings.[17]

The other improvement, a higher 400 MT/s bus clock, helped Barton gain some more efficiency. However, it was clear by this time that Intel's quad-pumped bus was scaling well above AMD's double-pumped EV7 bus. The 800 MT/s Pentium 4 bus was well out of Athlon's reach. In order to reach the same bandwidth levels, the Athlon bus would have to be clocked at levels simply unreachable.[16]

The K7 architecture had scaled to its limit. Maintaining performance equivalence with Intel's improving processors would require a significant redesign.[16] AMD would soon launch Athlon 64.

Specifications:
Barton (130 nm)

  • L1-Cache: 64 + 64 KiB (Data + Instructions)
  • L2-Cache: 512 KiB, fullspeed
  • MMX, 3DNow!, SSE
  • Socket A (EV6)
  • Front side bus: 166/200 MHz (333/400 MT/s)
  • VCore: 1.65 V
  • First release: February 10, 2003
  • Clockrate: 1833 - 2333 MHz (2500+ to 3200+)
    • 166 MHz FSB: 1833 - 2333 MHz (2500+ to 3200+)
    • 200 MHz FSB: 2100, 2200 MHz (3000+, 3200+)

Thorton (130 nm)

  • L1-Cache: 64 + 64 KiB (Data + Instructions)
  • L2-Cache: 256 KiB, fullspeed
  • MMX, 3DNow!, SSE
  • Socket A (EV6)
  • Front side bus: 133/166/200 MHz (266/333/400 MT/s)
  • VCore: 1.5 V - 1.65 V
  • First release: September 2003
  • Clockrate: 1667 - 2200 MHz (2000+ to 3100+)
    • 133 MHz FSB: 1600 - 2133 MHz (2000+ to 2600+)
    • 166 MHz FSB: 2083 MHz (2600+)
    • 200 MHz FSB: 2200 MHz (3100+)

[edit] Mobile Athlon XP

Athlon XP Mobile "Barton" 2400+
Athlon XP Mobile "Barton" 2400+

Mobile Athlon XPs (Athlon XP-M) are identical to normal Athlon XPs, apart from running at lower voltages, often lower bus speeds, and not being multiplier-locked. The lower Vcore rating caused the CPU to have lower power consumption (ideal for battery-powered laptops) and lower heat production. Athlon XP-M CPUs also have a higher-rated heat tolerance, a requirement of the tight conditions within a notebook PC.

The Athlon XP-M replaced the older Mobile Athlon 4. The Mobile Athlon 4 used the older Palomino core, while the Athlon XP-M used the newer Thoroughbred and Barton cores. Some specialized low-power Athlon XP-Ms utilize the microPGA socket 563 rather than the standard Socket A.

The CPUs, like their mobile K6+ predecessors, were also capable of dynamic clock adjustment for power optimization. When the system is idle, the CPU clocks itself down through a lower bus multiplier and also reduces its voltage. Then, when a program demands more computational resources, the CPU very quickly (there is some latency) returns to intermediate or maximum speed to meet the demand. This technology was marketed as "PowerNow!". It was similar to Intel's SpeedStep power saving technique. The feature was controlled by the CPU, motherboard BIOS, and operating system. AMD later renamed the technology to Cool'n'Quiet, on their K8-based CPUs (Athlon 64, etc), and re-imagined it for use on desktop PCs as well.

Athlon XP-Ms were popular with desktop overclockers, as well as underclockers. The lower voltage requirement and higher heat rating resulted in CPUs that were basically "cherry picked" from the manufacturing line. Being the best of the cores off the line, the CPUs typically were more reliably overclocked than their desktop-headed counterparts. Also, the fact that they weren't locked to a single multiplier was a significant simplification for the overclocking process. Some Barton core Athlon XP-Ms have been successfully overclocked to as high as 3.1 GHz.

As stated, the chips were also liked for their underclocking ability. Underclocking is a process of determining the lowest Vcore at which a CPU can remain stable at for a given clock speed. The Athlon XP-M CPUs were capable of running lower voltages per clock rate compared to their desktop siblings. As such, the chips were used in home theater PC systems due to their high performance and low heat output at low Vcore settings.

[edit] Athlon competitors

[edit] Supercomputers

The fastest supercomputers based on AthlonMP:

  • Rutgers University, Department of Physics & Astronomy. Machine: NOW Cluster - AMD Athlon. CPU: 512 AthlonMP (1.65 GHz). Rmax: 794 Gigaflops.
  • Athlon is the name of a family of CPUs designed by AMD, targeted mostly at the desktop market.

  • Athlon (Model 1,K7 "Argon", 250 nm)

    K7500MTR51B C, K7550MTR51B C and K7650MTR51B C

  • L2-Cache always runs with 50% of CPU speed
  • All models support: MMX, Enhanced 3DNow!
Model Number Frequency L2-Cache FSB 1 Multiplier Voltage TDP Socket Release Date Order Part Number
Athlon 500 500 MHz 512 KiB 200 MT/s 5x 1.60 V 42 W Slot A June 23, 1999
Athlon 550 550 MHz 512 KiB 200 MT/s 5.5x 1.60 V 46 W Slot A June 23, 1999
Athlon 600 600 MHz 512 KiB 200 MT/s 6x 1.60 V 50 W Slot A June 23, 1999
Athlon 650 650 MHz 512 KiB 200 MT/s 6.5x 1.60 V 54 W Slot A August 9, 1999
Athlon 700 700 MHz 512 KiB 200 MT/s 7x 1.60 V 50 W Slot A October 4, 1999

[edit] Athlon (Model 2, K75 "Pluto/Orion", 180 nm)

K7600MTR51B A, K7700MTR51B A, K7750MTR52B A, K7800MPR52B A and K7850MPR52B A

  • L2-Cache runs with 50% (up to 700 MHz), 40% (up to 850 MHz) or 33% (up to 1000 MHz) of CPU speed
  • All models support: MMX, Enhanced 3DNow!
Model Number Frequency L2-Cache FSB 1 Multiplier Voltage TDP Socket Release Date Order Part Number
Athlon 550 550 MHz 512 KiB 200 MT/s 5.5x 1.60 V 31 W Slot A November 29, 1999
Athlon 600 600 MHz 512 KiB 200 MT/s 6x 1.60 V 34 W Slot A November 29, 1999
Athlon 650 650 MHz 512 KiB 200 MT/s 6.5x 1.60 V 36 W Slot A November 29, 1999
Athlon 700 700 MHz 512 KiB 200 MT/s 7x 1.60 V 39 W Slot A November 29, 1999
Athlon 750 750 MHz 512 KiB 200 MT/s 7.5x 1.60 V 40 W Slot A November 29, 1999
Athlon 800 800 MHz 512 KiB 200 MT/s 8x 1.70 V 48 W Slot A January 6, 2000
Athlon 850 850 MHz 512 KiB 200 MT/s 8.5x 1.70 V 50 W Slot A February 11, 2000
Athlon 900 900 MHz 512 KiB 200 MT/s 9x 1.80 V 60 W Slot A March 6, 2000
Athlon 950 950 MHz 512 KiB 200 MT/s 9.5x 1.80 V 62 W Slot A March 6, 2000
Athlon 1000 1000 MHz 512 KiB 200 MT/s 10x 1.80 V 65 W Slot A March 6, 2000

[edit] Athlon (Model 4, "Thunderbird", 180 nm)

A0700MPR24B A, A0700APT3B, A0850AMT3B, A0900AMT3B, A1000AMT3B, A1100AMS3B, A1200AMS3C, A1300AMS3B, A1333AMS3C and A1400AMS3C

Model Number Frequency L2-Cache FSB 1 Multiplier Voltage TDP Socket Release Date Order Part Number
Athlon 600 600 MHz 256 KiB 200 MT/s 6x 1.75 V ??? Socket A, Slot A June 5, 2000 A0600AMT3B
Athlon 650 650 MHz 256 KiB 200 MT/s 6.5x 1.7/1.75 V 36.1/38 W Socket A, Slot A June 5, 2000 A0650AMT3B
A0650APT3B
Athlon 700 700 MHz 256 KiB 200 MT/s 7x 1.7/1.75 V 38.3/40 W Socket A, Slot A June 5, 2000 A0700AMT3B
A0700APT3B
Athlon 750 750 MHz 256 KiB 200 MT/s 7.5x 1.7/1.75 V 40.4/43 W Socket A, Slot A June 5, 2000 A0750AMT3B
Athlon 800 800 MHz 256 KiB 200 MT/s 8x 1.7/1.75 V 42.6/45 W Socket A, Slot A June 5, 2000 A0800AMT3B
A0800APT3B
Athlon 850 850 MHz 256 KiB 200 MT/s 8.5x 1.7/1.75 V 44.8/47 W Socket A, Slot A June 5, 2000 A0850AMT3B
A0850APT3B
Athlon 900 900 MHz 256 KiB 200 MT/s 9x 1.75 V 50 W Socket A, Slot A June 5, 2000 A0900AMT3B
A0900APT3B
Athlon 950 950 MHz 256 KiB 200 MT/s 9.5x 1.75 V 52 W Socket A, Slot A June 5, 2000 A0950AMT3B
Athlon 1000B 1000 MHz 256 KiB 200 MT/s 10x 1.75 V 54 W Socket A, Slot A June 5, 2000 A1000AMS3B
Athlon 1000C 1000 MHz 256 KiB 266 MT/s 7.5x 1.75 V 54 W Socket A October 31, 2000 A1000AMS3C
Athlon 1100B 1100 MHz 256 KiB 200 MT/s 11x 1.75 V 55.1/60 W Socket A August 14, 2000 A1100AMS3B
Athlon 1133C 1133 MHz 256 KiB 266 MT/s 8.5x 1.75 V 63 W Socket A October 31, 2000 A1133AMS3C
Athlon 1200B 1200 MHz 256 KiB 200 MT/s 12x 1.75 V 66 W Socket A October 17, 2000 A1200AMS3B
Athlon 1200C 1200 MHz 256 KiB 266 MT/s 9x 1.75 V 66 W Socket A October 31, 2000 A1200AMS3C
Athlon 1300B 1300 MHz 256 KiB 200 MT/s 13x 1.75 V 68 W Socket A March 21, 2001 A1300AMS3B
Athlon 1333C 1333 MHz 256 KiB 266 MT/s 10x 1.75 V 70 W Socket A March 21, 2001 A1333AMS3C
Athlon 1400B 1400 MHz 256 KiB 200 MT/s 14x 1.75 V 72 W Socket A June 6, 2001 A1400AMS3B
Athlon 1400C 1400 MHz 256 KiB 266 MT/s 10.5x 1.75 V 72
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